Whenever a single facility or resource is shared between two working units, it is possible that both working units, running independently, will attempt to access the shared resource simultaneously. This type of operation may be exemplified by the use of a dual-ported random-access memory (RAM).
A dual-ported RAM provides a means for multiprocessor systems to exchange data without directly interfering with each other. In many systems, this data exchange involves a master processing unit (MPU) passing information to a slave processing unit. For example, a host MPU may need to transfer information to a graphic processing unit to direct a display operation. Redundant processing schemes may require a checking processor to compare the results of several processors operating simultaneously. Whatever the application, some form of communication between processors is required.
As its name implies, a dual-ported RAM has two independent ports or address/data/control buses. An arbitration scheme is therefore required to allow two processors to access the same memory contents without interfering with each other. Thus, depending on the amount of dual-ported RAM that is available, messages, instructions, data, may be transferred from one processor to the other.
Access to a dual-ported RAM is usually controlled by one or more semaphore registers. A semaphore register is simply a memory location set aside as a flag to indicate whether or not a dual-ported RAM is currently in use. If the semaphore bit is set, one of the two processors is currently using the dual-ported RAM space and the other processor is not allowed access. Other semaphore registers could be defined to indicate messages available, contents changes, etc. . . .
A similar situation arises in duplicated telecommunication systems. For example, a digital data line module of a contemporary digital switching system may comprise a pair of processors, a plurality of port cards for communication to the outside world and a single digital port maintenance card for performing various maintenance functions. In this case, an arbitration circuit is necessary to regulate the exchange of control and data and prevent possible dual access to the maintenance card. Thus, by definition, a processor arbitration circuit has a request input lead from each of a pair of processors and a select enable lead to each processor.
The existing arbitration circuits are of the so-called synchronous type which require that all signals be referenced to a common or master clock; each processor unit has a select line asynchronous to this clock.
A number of often unrecognized problems are associated with the sampling of asynchronous signals with synchronous clock signals particularly at the operation speeds of contemporary circuitry. Any design of a processor arbitration circuit must consider the metastable conditions that may be generated.
Occasionally, outputs from a synchronized element, usually a D-type flip-flop, exhibit evidence of transient behaviour for periods longer than maximum propagation delays. This abnormality reflects metastable conditions.
An often overlooked point is that the D-type flip-flop itself is an asynchronous device with internal feedback. It is assumed that the output of the flip-flop will take one state or the other in a determinate amount of time independent of the D-input's timing relationship to the flip-flop's clock. However, a D-type flip-flop assumes fundamental mode operation only when the input signals change one at a time and when the circuit is in a stable condition. The duration of the uncertainty window brackets the clock edge which initiates state changes. Its dimensions are the specified setup and hold times of the device and somewhere in that window lies the actual metastable window that will cause the erratic output behaviour. Therefore, a metastable condition can occur any time a signal is random and asynchronous relative to a sampling clock or signal reference.
Metastability increases proportionally as the frequency of the incoming signal increases or as the frequency of the sampling clock increases. However, precautionary measures can be taken to minimize the effects of metastability. These include the avoidance of unnecessary synchronization, moving the asynchronous boundaries to the interface with the lowest possible speeds, and the use of asynchronous design techniques rather than synchronous techniques.
As mentioned above, the processor arbitration circuits presently in use are usually of the synchronous type. A pair of cascaded flip-flops is used for each request line and each pair of flip-flops is clocked with a respective one of clock and inverted clock signals. Since the clocking signals for the two portions of the circuit are 180 degrees apart, then one select signal will always appear on the output of the second flip-flop of one half of the circuit before the other, even during simultaneous access. The output of each second stage flip-flop feeds into the preset input of the other, thereby locking out the later incoming select request. A synchronous arbitration circuit thus requires a full clock cycle for the generation of a select enable at its output.
It is an object of the invention to provide an asynchronous arbitration circuit that does not require the use of clock signals and which can therefore respond to select requests from the processors substantially as they are received.